circuit AsyncQueue :
  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_1 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_2 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_3 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_4 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_6 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_7 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerShiftReg_w8_d3_i0 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<8>, q : UInt<8>}

    node _output_T = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_1 = bits(io.d, 0, 0) @[SynchronizerReg.scala 87:41]
    inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 @[ShiftReg.scala 45:23]
    output_chain.clock <= clock
    output_chain.reset <= _output_T
    output_chain.io.d <= _output_T_1 @[ShiftReg.scala 47:16]
    wire output_0 : UInt<1> @[ShiftReg.scala 48:24]
    output_0 <= output_chain.io.q @[ShiftReg.scala 48:24]
    node _output_T_2 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_3 = bits(io.d, 1, 1) @[SynchronizerReg.scala 87:41]
    inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_1 @[ShiftReg.scala 45:23]
    output_chain_1.clock <= clock
    output_chain_1.reset <= _output_T_2
    output_chain_1.io.d <= _output_T_3 @[ShiftReg.scala 47:16]
    wire output_1 : UInt<1> @[ShiftReg.scala 48:24]
    output_1 <= output_chain_1.io.q @[ShiftReg.scala 48:24]
    node _output_T_4 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_5 = bits(io.d, 2, 2) @[SynchronizerReg.scala 87:41]
    inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_2 @[ShiftReg.scala 45:23]
    output_chain_2.clock <= clock
    output_chain_2.reset <= _output_T_4
    output_chain_2.io.d <= _output_T_5 @[ShiftReg.scala 47:16]
    wire output_2 : UInt<1> @[ShiftReg.scala 48:24]
    output_2 <= output_chain_2.io.q @[ShiftReg.scala 48:24]
    node _output_T_6 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_7 = bits(io.d, 3, 3) @[SynchronizerReg.scala 87:41]
    inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_3 @[ShiftReg.scala 45:23]
    output_chain_3.clock <= clock
    output_chain_3.reset <= _output_T_6
    output_chain_3.io.d <= _output_T_7 @[ShiftReg.scala 47:16]
    wire output_3 : UInt<1> @[ShiftReg.scala 48:24]
    output_3 <= output_chain_3.io.q @[ShiftReg.scala 48:24]
    node _output_T_8 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_9 = bits(io.d, 4, 4) @[SynchronizerReg.scala 87:41]
    inst output_chain_4 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_4 @[ShiftReg.scala 45:23]
    output_chain_4.clock <= clock
    output_chain_4.reset <= _output_T_8
    output_chain_4.io.d <= _output_T_9 @[ShiftReg.scala 47:16]
    wire output_4 : UInt<1> @[ShiftReg.scala 48:24]
    output_4 <= output_chain_4.io.q @[ShiftReg.scala 48:24]
    node _output_T_10 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_11 = bits(io.d, 5, 5) @[SynchronizerReg.scala 87:41]
    inst output_chain_5 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5 @[ShiftReg.scala 45:23]
    output_chain_5.clock <= clock
    output_chain_5.reset <= _output_T_10
    output_chain_5.io.d <= _output_T_11 @[ShiftReg.scala 47:16]
    wire output_5 : UInt<1> @[ShiftReg.scala 48:24]
    output_5 <= output_chain_5.io.q @[ShiftReg.scala 48:24]
    node _output_T_12 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_13 = bits(io.d, 6, 6) @[SynchronizerReg.scala 87:41]
    inst output_chain_6 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_6 @[ShiftReg.scala 45:23]
    output_chain_6.clock <= clock
    output_chain_6.reset <= _output_T_12
    output_chain_6.io.d <= _output_T_13 @[ShiftReg.scala 47:16]
    wire output_6 : UInt<1> @[ShiftReg.scala 48:24]
    output_6 <= output_chain_6.io.q @[ShiftReg.scala 48:24]
    node _output_T_14 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_15 = bits(io.d, 7, 7) @[SynchronizerReg.scala 87:41]
    inst output_chain_7 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_7 @[ShiftReg.scala 45:23]
    output_chain_7.clock <= clock
    output_chain_7.reset <= _output_T_14
    output_chain_7.io.d <= _output_T_15 @[ShiftReg.scala 47:16]
    wire output_7 : UInt<1> @[ShiftReg.scala 48:24]
    output_7 <= output_chain_7.io.q @[ShiftReg.scala 48:24]
    node io_q_lo_lo = cat(output_1, output_0) @[Cat.scala 33:92]
    node io_q_lo_hi = cat(output_3, output_2) @[Cat.scala 33:92]
    node io_q_lo = cat(io_q_lo_hi, io_q_lo_lo) @[Cat.scala 33:92]
    node io_q_hi_lo = cat(output_5, output_4) @[Cat.scala 33:92]
    node io_q_hi_hi = cat(output_7, output_6) @[Cat.scala 33:92]
    node io_q_hi = cat(io_q_hi_hi, io_q_hi_lo) @[Cat.scala 33:92]
    node _io_q_T = cat(io_q_hi, io_q_lo) @[Cat.scala 33:92]
    io.q <= _io_q_T @[SynchronizerReg.scala 90:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_8 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerShiftReg_w1_d3_i0 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<1>, q : UInt<1>}

    node _output_T = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_1 = bits(io.d, 0, 0) @[SynchronizerReg.scala 87:41]
    inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_8 @[ShiftReg.scala 45:23]
    output_chain.clock <= clock
    output_chain.reset <= _output_T
    output_chain.io.d <= _output_T_1 @[ShiftReg.scala 47:16]
    wire output_0 : UInt<1> @[ShiftReg.scala 48:24]
    output_0 <= output_chain.io.q @[ShiftReg.scala 48:24]
    io.q <= output_0 @[SynchronizerReg.scala 90:8]

  module AsyncValidSync :
    output io : { flip in : UInt<1>, out : UInt<1>}
    input clock : Clock
    input reset : AsyncReset

    inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0 @[ShiftReg.scala 45:23]
    io_out_source_valid_0.clock <= clock
    io_out_source_valid_0.reset <= reset
    io_out_source_valid_0.io.d <= io.in @[ShiftReg.scala 47:16]
    wire _io_out_WIRE : UInt<1> @[ShiftReg.scala 48:24]
    _io_out_WIRE <= io_out_source_valid_0.io.q @[ShiftReg.scala 48:24]
    io.out <= _io_out_WIRE @[AsyncQueue.scala 66:12]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_9 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerShiftReg_w1_d3_i0_1 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<1>, q : UInt<1>}

    node _output_T = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_1 = bits(io.d, 0, 0) @[SynchronizerReg.scala 87:41]
    inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_9 @[ShiftReg.scala 45:23]
    output_chain.clock <= clock
    output_chain.reset <= _output_T
    output_chain.io.d <= _output_T_1 @[ShiftReg.scala 47:16]
    wire output_0 : UInt<1> @[ShiftReg.scala 48:24]
    output_0 <= output_chain.io.q @[ShiftReg.scala 48:24]
    io.q <= output_0 @[SynchronizerReg.scala 90:8]

  module AsyncValidSync_1 :
    output io : { flip in : UInt<1>, out : UInt<1>}
    input clock : Clock
    input reset : AsyncReset

    inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_1 @[ShiftReg.scala 45:23]
    io_out_source_valid_1.clock <= clock
    io_out_source_valid_1.reset <= reset
    io_out_source_valid_1.io.d <= io.in @[ShiftReg.scala 47:16]
    wire _io_out_WIRE : UInt<1> @[ShiftReg.scala 48:24]
    _io_out_WIRE <= io_out_source_valid_1.io.q @[ShiftReg.scala 48:24]
    io.out <= _io_out_WIRE @[AsyncQueue.scala 66:12]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_10 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerShiftReg_w1_d3_i0_2 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<1>, q : UInt<1>}

    node _output_T = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_1 = bits(io.d, 0, 0) @[SynchronizerReg.scala 87:41]
    inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_10 @[ShiftReg.scala 45:23]
    output_chain.clock <= clock
    output_chain.reset <= _output_T
    output_chain.io.d <= _output_T_1 @[ShiftReg.scala 47:16]
    wire output_0 : UInt<1> @[ShiftReg.scala 48:24]
    output_0 <= output_chain.io.q @[ShiftReg.scala 48:24]
    io.q <= output_0 @[SynchronizerReg.scala 90:8]

  module AsyncValidSync_2 :
    output io : { flip in : UInt<1>, out : UInt<1>}
    input clock : Clock
    input reset : AsyncReset

    inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_2 @[ShiftReg.scala 45:23]
    io_out_sink_extend.clock <= clock
    io_out_sink_extend.reset <= reset
    io_out_sink_extend.io.d <= io.in @[ShiftReg.scala 47:16]
    wire _io_out_WIRE : UInt<1> @[ShiftReg.scala 48:24]
    _io_out_WIRE <= io_out_sink_extend.io.q @[ShiftReg.scala 48:24]
    io.out <= _io_out_WIRE @[AsyncQueue.scala 66:12]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_11 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerShiftReg_w1_d3_i0_3 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<1>, q : UInt<1>}

    node _output_T = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_1 = bits(io.d, 0, 0) @[SynchronizerReg.scala 87:41]
    inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_11 @[ShiftReg.scala 45:23]
    output_chain.clock <= clock
    output_chain.reset <= _output_T
    output_chain.io.d <= _output_T_1 @[ShiftReg.scala 47:16]
    wire output_0 : UInt<1> @[ShiftReg.scala 48:24]
    output_0 <= output_chain.io.q @[ShiftReg.scala 48:24]
    io.q <= output_0 @[SynchronizerReg.scala 90:8]

  module AsyncValidSync_3 :
    output io : { flip in : UInt<1>, out : UInt<1>}
    input clock : Clock
    input reset : AsyncReset

    inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_3 @[ShiftReg.scala 45:23]
    io_out_sink_valid.clock <= clock
    io_out_sink_valid.reset <= reset
    io_out_sink_valid.io.d <= io.in @[ShiftReg.scala 47:16]
    wire _io_out_WIRE : UInt<1> @[ShiftReg.scala 48:24]
    _io_out_WIRE <= io_out_sink_valid.io.q @[ShiftReg.scala 48:24]
    io.out <= _io_out_WIRE @[AsyncQueue.scala 66:12]

  module AsyncQueueSource :
    input clock : Clock
    input reset : Reset
    output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, async : { mem : UInt<32>[128], flip ridx : UInt<8>, widx : UInt<8>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}

    wire sink_ready : UInt<1>
    sink_ready <= UInt<1>("h1")
    reg mem : UInt<32>[128], clock with :
      reset => (UInt<1>("h0"), mem) @[AsyncQueue.scala 80:16]
    node _widx_T = asAsyncReset(reset) @[AsyncQueue.scala 81:30]
    node _widx_T_1 = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 52:35]
    node _widx_T_2 = eq(sink_ready, UInt<1>("h0")) @[AsyncQueue.scala 81:79]
    wire widx_incremented : UInt<8> @[AsyncQueue.scala 51:27]
    reg widx_widx_bin : UInt, clock with :
      reset => (_widx_T, UInt<1>("h0")) @[AsyncQueue.scala 52:25]
    widx_widx_bin <= widx_incremented @[AsyncQueue.scala 52:25]
    node _widx_incremented_T = add(widx_widx_bin, _widx_T_1) @[AsyncQueue.scala 53:43]
    node _widx_incremented_T_1 = tail(_widx_incremented_T, 1) @[AsyncQueue.scala 53:43]
    node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>("h0"), _widx_incremented_T_1) @[AsyncQueue.scala 53:23]
    widx_incremented <= _widx_incremented_T_2 @[AsyncQueue.scala 53:17]
    node _widx_T_3 = shr(widx_incremented, 1) @[AsyncQueue.scala 54:32]
    node widx = xor(widx_incremented, _widx_T_3) @[AsyncQueue.scala 54:17]
    inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w8_d3_i0 @[ShiftReg.scala 45:23]
    ridx_ridx_gray.clock <= clock
    ridx_ridx_gray.reset <= reset
    ridx_ridx_gray.io.d <= io.async.ridx @[ShiftReg.scala 47:16]
    wire ridx : UInt<8> @[ShiftReg.scala 48:24]
    ridx <= ridx_ridx_gray.io.q @[ShiftReg.scala 48:24]
    node _ready_T = xor(ridx, UInt<8>("hc0")) @[AsyncQueue.scala 83:44]
    node _ready_T_1 = neq(widx, _ready_T) @[AsyncQueue.scala 83:34]
    node ready = and(sink_ready, _ready_T_1) @[AsyncQueue.scala 83:26]
    node _index_T = bits(io.async.widx, 6, 0) @[AsyncQueue.scala 85:52]
    node _index_T_1 = bits(io.async.widx, 7, 7) @[AsyncQueue.scala 85:80]
    node _index_T_2 = shl(_index_T_1, 6) @[AsyncQueue.scala 85:93]
    node index = xor(_index_T, _index_T_2) @[AsyncQueue.scala 85:64]
    node _T = and(io.enq.ready, io.enq.valid) @[Decoupled.scala 52:35]
    when _T : @[AsyncQueue.scala 86:24]
      mem[index] <= io.enq.bits @[AsyncQueue.scala 86:37]
    node _ready_reg_T = asAsyncReset(reset) @[AsyncQueue.scala 88:35]
    reg ready_reg : UInt<1>, clock with :
      reset => (_ready_reg_T, UInt<1>("h0")) @[AsyncQueue.scala 88:56]
    ready_reg <= ready @[AsyncQueue.scala 88:56]
    node _io_enq_ready_T = and(ready_reg, sink_ready) @[AsyncQueue.scala 89:29]
    io.enq.ready <= _io_enq_ready_T @[AsyncQueue.scala 89:16]
    node _widx_reg_T = asAsyncReset(reset) @[AsyncQueue.scala 91:34]
    reg widx_gray : UInt, clock with :
      reset => (_widx_reg_T, UInt<1>("h0")) @[AsyncQueue.scala 91:55]
    widx_gray <= widx @[AsyncQueue.scala 91:55]
    io.async.widx <= widx_gray @[AsyncQueue.scala 92:17]
    io.async.mem <= mem @[AsyncQueue.scala 96:31]
    inst source_valid_0 of AsyncValidSync @[AsyncQueue.scala 100:32]
    inst source_valid_1 of AsyncValidSync_1 @[AsyncQueue.scala 101:32]
    inst sink_extend of AsyncValidSync_2 @[AsyncQueue.scala 103:30]
    inst sink_valid of AsyncValidSync_3 @[AsyncQueue.scala 104:30]
    node _source_valid_0_reset_T = asUInt(reset) @[AsyncQueue.scala 105:36]
    node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>("h0")) @[AsyncQueue.scala 105:46]
    node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1) @[AsyncQueue.scala 105:43]
    node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2) @[AsyncQueue.scala 105:65]
    source_valid_0.reset <= _source_valid_0_reset_T_3 @[AsyncQueue.scala 105:26]
    node _source_valid_1_reset_T = asUInt(reset) @[AsyncQueue.scala 106:36]
    node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>("h0")) @[AsyncQueue.scala 106:46]
    node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1) @[AsyncQueue.scala 106:43]
    node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2) @[AsyncQueue.scala 106:65]
    source_valid_1.reset <= _source_valid_1_reset_T_3 @[AsyncQueue.scala 106:26]
    node _sink_extend_reset_T = asUInt(reset) @[AsyncQueue.scala 107:36]
    node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>("h0")) @[AsyncQueue.scala 107:46]
    node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1) @[AsyncQueue.scala 107:43]
    node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2) @[AsyncQueue.scala 107:65]
    sink_extend.reset <= _sink_extend_reset_T_3 @[AsyncQueue.scala 107:26]
    node _sink_valid_reset_T = asAsyncReset(reset) @[AsyncQueue.scala 108:35]
    sink_valid.reset <= _sink_valid_reset_T @[AsyncQueue.scala 108:26]
    source_valid_0.clock <= clock @[AsyncQueue.scala 110:26]
    source_valid_1.clock <= clock @[AsyncQueue.scala 111:26]
    sink_extend.clock <= clock @[AsyncQueue.scala 112:26]
    sink_valid.clock <= clock @[AsyncQueue.scala 113:26]
    source_valid_0.io.in <= UInt<1>("h1") @[AsyncQueue.scala 115:26]
    source_valid_1.io.in <= source_valid_0.io.out @[AsyncQueue.scala 116:26]
    io.async.safe.widx_valid <= source_valid_1.io.out @[AsyncQueue.scala 117:20]
    sink_extend.io.in <= io.async.safe.ridx_valid @[AsyncQueue.scala 118:23]
    sink_valid.io.in <= sink_extend.io.out @[AsyncQueue.scala 119:22]
    sink_ready <= sink_valid.io.out @[AsyncQueue.scala 120:16]
    node _io_async_safe_source_reset_n_T = asUInt(reset) @[AsyncQueue.scala 121:34]
    node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>("h0")) @[AsyncQueue.scala 121:27]
    io.async.safe.source_reset_n <= _io_async_safe_source_reset_n_T_1 @[AsyncQueue.scala 121:24]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_12 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_13 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_14 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_15 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_16 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_17 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_18 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_19 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerShiftReg_w8_d3_i0_1 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<8>, q : UInt<8>}

    node _output_T = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_1 = bits(io.d, 0, 0) @[SynchronizerReg.scala 87:41]
    inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_12 @[ShiftReg.scala 45:23]
    output_chain.clock <= clock
    output_chain.reset <= _output_T
    output_chain.io.d <= _output_T_1 @[ShiftReg.scala 47:16]
    wire output_0 : UInt<1> @[ShiftReg.scala 48:24]
    output_0 <= output_chain.io.q @[ShiftReg.scala 48:24]
    node _output_T_2 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_3 = bits(io.d, 1, 1) @[SynchronizerReg.scala 87:41]
    inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_13 @[ShiftReg.scala 45:23]
    output_chain_1.clock <= clock
    output_chain_1.reset <= _output_T_2
    output_chain_1.io.d <= _output_T_3 @[ShiftReg.scala 47:16]
    wire output_1 : UInt<1> @[ShiftReg.scala 48:24]
    output_1 <= output_chain_1.io.q @[ShiftReg.scala 48:24]
    node _output_T_4 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_5 = bits(io.d, 2, 2) @[SynchronizerReg.scala 87:41]
    inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_14 @[ShiftReg.scala 45:23]
    output_chain_2.clock <= clock
    output_chain_2.reset <= _output_T_4
    output_chain_2.io.d <= _output_T_5 @[ShiftReg.scala 47:16]
    wire output_2 : UInt<1> @[ShiftReg.scala 48:24]
    output_2 <= output_chain_2.io.q @[ShiftReg.scala 48:24]
    node _output_T_6 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_7 = bits(io.d, 3, 3) @[SynchronizerReg.scala 87:41]
    inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_15 @[ShiftReg.scala 45:23]
    output_chain_3.clock <= clock
    output_chain_3.reset <= _output_T_6
    output_chain_3.io.d <= _output_T_7 @[ShiftReg.scala 47:16]
    wire output_3 : UInt<1> @[ShiftReg.scala 48:24]
    output_3 <= output_chain_3.io.q @[ShiftReg.scala 48:24]
    node _output_T_8 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_9 = bits(io.d, 4, 4) @[SynchronizerReg.scala 87:41]
    inst output_chain_4 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_16 @[ShiftReg.scala 45:23]
    output_chain_4.clock <= clock
    output_chain_4.reset <= _output_T_8
    output_chain_4.io.d <= _output_T_9 @[ShiftReg.scala 47:16]
    wire output_4 : UInt<1> @[ShiftReg.scala 48:24]
    output_4 <= output_chain_4.io.q @[ShiftReg.scala 48:24]
    node _output_T_10 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_11 = bits(io.d, 5, 5) @[SynchronizerReg.scala 87:41]
    inst output_chain_5 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_17 @[ShiftReg.scala 45:23]
    output_chain_5.clock <= clock
    output_chain_5.reset <= _output_T_10
    output_chain_5.io.d <= _output_T_11 @[ShiftReg.scala 47:16]
    wire output_5 : UInt<1> @[ShiftReg.scala 48:24]
    output_5 <= output_chain_5.io.q @[ShiftReg.scala 48:24]
    node _output_T_12 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_13 = bits(io.d, 6, 6) @[SynchronizerReg.scala 87:41]
    inst output_chain_6 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_18 @[ShiftReg.scala 45:23]
    output_chain_6.clock <= clock
    output_chain_6.reset <= _output_T_12
    output_chain_6.io.d <= _output_T_13 @[ShiftReg.scala 47:16]
    wire output_6 : UInt<1> @[ShiftReg.scala 48:24]
    output_6 <= output_chain_6.io.q @[ShiftReg.scala 48:24]
    node _output_T_14 = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_15 = bits(io.d, 7, 7) @[SynchronizerReg.scala 87:41]
    inst output_chain_7 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_19 @[ShiftReg.scala 45:23]
    output_chain_7.clock <= clock
    output_chain_7.reset <= _output_T_14
    output_chain_7.io.d <= _output_T_15 @[ShiftReg.scala 47:16]
    wire output_7 : UInt<1> @[ShiftReg.scala 48:24]
    output_7 <= output_chain_7.io.q @[ShiftReg.scala 48:24]
    node io_q_lo_lo = cat(output_1, output_0) @[Cat.scala 33:92]
    node io_q_lo_hi = cat(output_3, output_2) @[Cat.scala 33:92]
    node io_q_lo = cat(io_q_lo_hi, io_q_lo_lo) @[Cat.scala 33:92]
    node io_q_hi_lo = cat(output_5, output_4) @[Cat.scala 33:92]
    node io_q_hi_hi = cat(output_7, output_6) @[Cat.scala 33:92]
    node io_q_hi = cat(io_q_hi_hi, io_q_hi_lo) @[Cat.scala 33:92]
    node _io_q_T = cat(io_q_hi, io_q_lo) @[Cat.scala 33:92]
    io.q <= _io_q_T @[SynchronizerReg.scala 90:8]

  module ClockCrossingReg_w32 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<32>, q : UInt<32>, flip en : UInt<1>}

    reg cdc_reg : UInt<32>, clock with :
      reset => (UInt<1>("h0"), cdc_reg) @[Reg.scala 19:16]
    when io.en : @[Reg.scala 20:18]
      cdc_reg <= io.d @[Reg.scala 20:22]
    io.q <= cdc_reg @[SynchronizerReg.scala 202:8]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_20 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerShiftReg_w1_d3_i0_4 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<1>, q : UInt<1>}

    node _output_T = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_1 = bits(io.d, 0, 0) @[SynchronizerReg.scala 87:41]
    inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_20 @[ShiftReg.scala 45:23]
    output_chain.clock <= clock
    output_chain.reset <= _output_T
    output_chain.io.d <= _output_T_1 @[ShiftReg.scala 47:16]
    wire output_0 : UInt<1> @[ShiftReg.scala 48:24]
    output_0 <= output_chain.io.q @[ShiftReg.scala 48:24]
    io.q <= output_0 @[SynchronizerReg.scala 90:8]

  module AsyncValidSync_4 :
    output io : { flip in : UInt<1>, out : UInt<1>}
    input clock : Clock
    input reset : AsyncReset

    inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_4 @[ShiftReg.scala 45:23]
    io_out_sink_valid_0.clock <= clock
    io_out_sink_valid_0.reset <= reset
    io_out_sink_valid_0.io.d <= io.in @[ShiftReg.scala 47:16]
    wire _io_out_WIRE : UInt<1> @[ShiftReg.scala 48:24]
    _io_out_WIRE <= io_out_sink_valid_0.io.q @[ShiftReg.scala 48:24]
    io.out <= _io_out_WIRE @[AsyncQueue.scala 66:12]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_21 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerShiftReg_w1_d3_i0_5 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<1>, q : UInt<1>}

    node _output_T = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_1 = bits(io.d, 0, 0) @[SynchronizerReg.scala 87:41]
    inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_21 @[ShiftReg.scala 45:23]
    output_chain.clock <= clock
    output_chain.reset <= _output_T
    output_chain.io.d <= _output_T_1 @[ShiftReg.scala 47:16]
    wire output_0 : UInt<1> @[ShiftReg.scala 48:24]
    output_0 <= output_chain.io.q @[ShiftReg.scala 48:24]
    io.q <= output_0 @[SynchronizerReg.scala 90:8]

  module AsyncValidSync_5 :
    output io : { flip in : UInt<1>, out : UInt<1>}
    input clock : Clock
    input reset : AsyncReset

    inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_5 @[ShiftReg.scala 45:23]
    io_out_sink_valid_1.clock <= clock
    io_out_sink_valid_1.reset <= reset
    io_out_sink_valid_1.io.d <= io.in @[ShiftReg.scala 47:16]
    wire _io_out_WIRE : UInt<1> @[ShiftReg.scala 48:24]
    _io_out_WIRE <= io_out_sink_valid_1.io.q @[ShiftReg.scala 48:24]
    io.out <= _io_out_WIRE @[AsyncQueue.scala 66:12]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_22 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerShiftReg_w1_d3_i0_6 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<1>, q : UInt<1>}

    node _output_T = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_1 = bits(io.d, 0, 0) @[SynchronizerReg.scala 87:41]
    inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_22 @[ShiftReg.scala 45:23]
    output_chain.clock <= clock
    output_chain.reset <= _output_T
    output_chain.io.d <= _output_T_1 @[ShiftReg.scala 47:16]
    wire output_0 : UInt<1> @[ShiftReg.scala 48:24]
    output_0 <= output_chain.io.q @[ShiftReg.scala 48:24]
    io.q <= output_0 @[SynchronizerReg.scala 90:8]

  module AsyncValidSync_6 :
    output io : { flip in : UInt<1>, out : UInt<1>}
    input clock : Clock
    input reset : AsyncReset

    inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_6 @[ShiftReg.scala 45:23]
    io_out_source_extend.clock <= clock
    io_out_source_extend.reset <= reset
    io_out_source_extend.io.d <= io.in @[ShiftReg.scala 47:16]
    wire _io_out_WIRE : UInt<1> @[ShiftReg.scala 48:24]
    _io_out_WIRE <= io_out_source_extend.io.q @[ShiftReg.scala 48:24]
    io.out <= _io_out_WIRE @[AsyncQueue.scala 66:12]

  module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_23 :
    input clock : Clock
    input reset : AsyncReset
    output io : { flip d : UInt<1>, q : UInt<1>}

    reg sync_0 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_1 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    reg sync_2 : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[SynchronizerReg.scala 51:87]
    node _sync_2_T = bits(io.d, 0, 0) @[SynchronizerReg.scala 54:22]
    sync_2 <= _sync_2_T @[SynchronizerReg.scala 54:14]
    sync_0 <= sync_1 @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2 @[SynchronizerReg.scala 57:10]
    io.q <= sync_0 @[SynchronizerReg.scala 59:8]

  module AsyncResetSynchronizerShiftReg_w1_d3_i0_7 :
    input clock : Clock
    input reset : Reset
    output io : { flip d : UInt<1>, q : UInt<1>}

    node _output_T = asAsyncReset(reset) @[SynchronizerReg.scala 86:21]
    node _output_T_1 = bits(io.d, 0, 0) @[SynchronizerReg.scala 87:41]
    inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_23 @[ShiftReg.scala 45:23]
    output_chain.clock <= clock
    output_chain.reset <= _output_T
    output_chain.io.d <= _output_T_1 @[ShiftReg.scala 47:16]
    wire output_0 : UInt<1> @[ShiftReg.scala 48:24]
    output_0 <= output_chain.io.q @[ShiftReg.scala 48:24]
    io.q <= output_0 @[SynchronizerReg.scala 90:8]

  module AsyncValidSync_7 :
    output io : { flip in : UInt<1>, out : UInt<1>}
    input clock : Clock
    input reset : AsyncReset

    inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_7 @[ShiftReg.scala 45:23]
    io_out_source_valid.clock <= clock
    io_out_source_valid.reset <= reset
    io_out_source_valid.io.d <= io.in @[ShiftReg.scala 47:16]
    wire _io_out_WIRE : UInt<1> @[ShiftReg.scala 48:24]
    _io_out_WIRE <= io_out_source_valid.io.q @[ShiftReg.scala 48:24]
    io.out <= _io_out_WIRE @[AsyncQueue.scala 66:12]

  module AsyncQueueSink :
    input clock : Clock
    input reset : Reset
    output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, flip async : { mem : UInt<32>[128], flip ridx : UInt<8>, widx : UInt<8>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}

    wire source_ready : UInt<1>
    source_ready <= UInt<1>("h1")
    node _ridx_T = asAsyncReset(reset) @[AsyncQueue.scala 144:30]
    node _ridx_T_1 = and(io.deq.ready, io.deq.valid) @[Decoupled.scala 52:35]
    node _ridx_T_2 = eq(source_ready, UInt<1>("h0")) @[AsyncQueue.scala 144:79]
    wire ridx_incremented : UInt<8> @[AsyncQueue.scala 51:27]
    reg ridx_ridx_bin : UInt, clock with :
      reset => (_ridx_T, UInt<1>("h0")) @[AsyncQueue.scala 52:25]
    ridx_ridx_bin <= ridx_incremented @[AsyncQueue.scala 52:25]
    node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) @[AsyncQueue.scala 53:43]
    node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) @[AsyncQueue.scala 53:43]
    node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>("h0"), _ridx_incremented_T_1) @[AsyncQueue.scala 53:23]
    ridx_incremented <= _ridx_incremented_T_2 @[AsyncQueue.scala 53:17]
    node _ridx_T_3 = shr(ridx_incremented, 1) @[AsyncQueue.scala 54:32]
    node ridx = xor(ridx_incremented, _ridx_T_3) @[AsyncQueue.scala 54:17]
    inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w8_d3_i0_1 @[ShiftReg.scala 45:23]
    widx_widx_gray.clock <= clock
    widx_widx_gray.reset <= reset
    widx_widx_gray.io.d <= io.async.widx @[ShiftReg.scala 47:16]
    wire widx : UInt<8> @[ShiftReg.scala 48:24]
    widx <= widx_widx_gray.io.q @[ShiftReg.scala 48:24]
    node _valid_T = neq(ridx, widx) @[AsyncQueue.scala 146:36]
    node valid = and(source_ready, _valid_T) @[AsyncQueue.scala 146:28]
    node _index_T = bits(ridx, 6, 0) @[AsyncQueue.scala 152:43]
    node _index_T_1 = bits(ridx, 7, 7) @[AsyncQueue.scala 152:62]
    node _index_T_2 = shl(_index_T_1, 6) @[AsyncQueue.scala 152:75]
    node index = xor(_index_T, _index_T_2) @[AsyncQueue.scala 152:55]
    inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w32 @[SynchronizerReg.scala 207:25]
    io_deq_bits_deq_bits_reg.clock <= clock
    io_deq_bits_deq_bits_reg.reset <= reset
    io_deq_bits_deq_bits_reg.io.d <= io.async.mem[index] @[SynchronizerReg.scala 209:18]
    io_deq_bits_deq_bits_reg.io.en <= valid @[SynchronizerReg.scala 210:19]
    wire _io_deq_bits_WIRE : UInt<32> @[SynchronizerReg.scala 211:26]
    _io_deq_bits_WIRE <= io_deq_bits_deq_bits_reg.io.q @[SynchronizerReg.scala 211:26]
    io.deq.bits <= _io_deq_bits_WIRE @[AsyncQueue.scala 159:15]
    node _valid_reg_T = asAsyncReset(reset) @[AsyncQueue.scala 161:35]
    reg valid_reg : UInt<1>, clock with :
      reset => (_valid_reg_T, UInt<1>("h0")) @[AsyncQueue.scala 161:56]
    valid_reg <= valid @[AsyncQueue.scala 161:56]
    node _io_deq_valid_T = and(valid_reg, source_ready) @[AsyncQueue.scala 162:29]
    io.deq.valid <= _io_deq_valid_T @[AsyncQueue.scala 162:16]
    node _ridx_reg_T = asAsyncReset(reset) @[AsyncQueue.scala 164:34]
    reg ridx_gray : UInt, clock with :
      reset => (_ridx_reg_T, UInt<1>("h0")) @[AsyncQueue.scala 164:55]
    ridx_gray <= ridx @[AsyncQueue.scala 164:55]
    io.async.ridx <= ridx_gray @[AsyncQueue.scala 165:17]
    inst sink_valid_0 of AsyncValidSync_4 @[AsyncQueue.scala 168:33]
    inst sink_valid_1 of AsyncValidSync_5 @[AsyncQueue.scala 169:33]
    inst source_extend of AsyncValidSync_6 @[AsyncQueue.scala 171:31]
    inst source_valid of AsyncValidSync_7 @[AsyncQueue.scala 172:31]
    node _sink_valid_0_reset_T = asUInt(reset) @[AsyncQueue.scala 173:35]
    node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>("h0")) @[AsyncQueue.scala 173:45]
    node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) @[AsyncQueue.scala 173:42]
    node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) @[AsyncQueue.scala 173:66]
    sink_valid_0.reset <= _sink_valid_0_reset_T_3 @[AsyncQueue.scala 173:25]
    node _sink_valid_1_reset_T = asUInt(reset) @[AsyncQueue.scala 174:35]
    node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>("h0")) @[AsyncQueue.scala 174:45]
    node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) @[AsyncQueue.scala 174:42]
    node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) @[AsyncQueue.scala 174:66]
    sink_valid_1.reset <= _sink_valid_1_reset_T_3 @[AsyncQueue.scala 174:25]
    node _source_extend_reset_T = asUInt(reset) @[AsyncQueue.scala 175:35]
    node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>("h0")) @[AsyncQueue.scala 175:45]
    node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) @[AsyncQueue.scala 175:42]
    node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) @[AsyncQueue.scala 175:66]
    source_extend.reset <= _source_extend_reset_T_3 @[AsyncQueue.scala 175:25]
    node _source_valid_reset_T = asAsyncReset(reset) @[AsyncQueue.scala 176:34]
    source_valid.reset <= _source_valid_reset_T @[AsyncQueue.scala 176:25]
    sink_valid_0.clock <= clock @[AsyncQueue.scala 178:25]
    sink_valid_1.clock <= clock @[AsyncQueue.scala 179:25]
    source_extend.clock <= clock @[AsyncQueue.scala 180:25]
    source_valid.clock <= clock @[AsyncQueue.scala 181:25]
    sink_valid_0.io.in <= UInt<1>("h1") @[AsyncQueue.scala 183:24]
    sink_valid_1.io.in <= sink_valid_0.io.out @[AsyncQueue.scala 184:24]
    io.async.safe.ridx_valid <= sink_valid_1.io.out @[AsyncQueue.scala 185:20]
    source_extend.io.in <= io.async.safe.widx_valid @[AsyncQueue.scala 186:25]
    source_valid.io.in <= source_extend.io.out @[AsyncQueue.scala 187:24]
    source_ready <= source_valid.io.out @[AsyncQueue.scala 188:18]
    node _io_async_safe_sink_reset_n_T = asUInt(reset) @[AsyncQueue.scala 189:32]
    node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>("h0")) @[AsyncQueue.scala 189:25]
    io.async.safe.sink_reset_n <= _io_async_safe_sink_reset_n_T_1 @[AsyncQueue.scala 189:22]

  module AsyncQueue :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip enq_clock : Clock, flip enq_reset : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, flip deq_clock : Clock, flip deq_reset : UInt<1>, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}

    clock is invalid
    reset is invalid
    io is invalid
    inst source of AsyncQueueSource @[AsyncQueue.scala 224:22]
    source.clock <= clock
    source.reset <= reset
    inst sink of AsyncQueueSink @[AsyncQueue.scala 225:22]
    sink.clock <= clock
    sink.reset <= reset
    source.clock <= io.enq_clock @[AsyncQueue.scala 227:16]
    source.reset <= io.enq_reset @[AsyncQueue.scala 228:16]
    sink.clock <= io.deq_clock @[AsyncQueue.scala 229:14]
    sink.reset <= io.deq_reset @[AsyncQueue.scala 230:14]
    source.io.enq <= io.enq @[AsyncQueue.scala 232:17]
    io.deq.bits <= sink.io.deq.bits @[AsyncQueue.scala 233:10]
    io.deq.valid <= sink.io.deq.valid @[AsyncQueue.scala 233:10]
    sink.io.deq.ready <= io.deq.ready @[AsyncQueue.scala 233:10]
    sink.io.async <= source.io.async @[AsyncQueue.scala 234:17]

